1. Field
Example embodiments relate to a vertical type semiconductor device and a method of manufacturing a vertical type semiconductor device. More particularly, example embodiments relate to a vertical type semiconductor device having a multi-channel and a method of manufacturing a vertical type semiconductor device having a multi-channel.
2. Description of the Related Art
An active region becomes small according to a higher integration of a semiconductor device, so that a channel length of a MOS transistor formed in the active region may be reduced. When the channel length of a MOS transistor becomes small, a source/drain region has an effect on an electric field or an electric potential of the channel region, which may be called a short channel effect. When the short channel effect is generated, a leakage current may be increased, a breakdown voltage may be lowered and a current affected by a drain may be increased. As a result, the MOS transistor may be difficult to be controlled by a gate.
Many methods for reducing a size of devices formed on a substrate and maximizing or increasing performance of the devices have been developed. For example, a vertical type semiconductor device of which a channel may be formed along a direction substantially perpendicular to a substrate has been developed. The vertical type semiconductor device uses a semiconductor pattern of a pillar shape (hereinafter, a semiconductor pillar) on a substrate as a channel region. The vertical type semiconductor device may adjust a channel length by increasing the semiconductor pillar instead of increasing a horizontal area of the substrate.
In the vertical type semiconductor device, reducing a width of the semiconductor pillar may be needed for reducing a leakage current and obtaining a higher integration degree. However, when the width of the semiconductor pillar is reduced, a channel region formed through the semiconductor pillar may also be decreased. As a result, on-current of the vertical type semiconductor device may be reduced when the width of the semiconductor pillar is reduced.